VH2V
Convert VHDL entities into Verilog modules with GHDL and Yosys.
VH2V converts a VHDL file containing multiple entities into separate Verilog module files. A single Python script coordinates GHDL, Yosys, and the ghdl-yosys plugin.
Usage
python3 vh2v.py --input_file SystolicArray.vhdl --output_dir /tmp
The Python wrapper has no third-party Python dependencies. GHDL, Yosys, and the plugin must be installed separately; the README describes that toolchain.
I used this conversion path for the wrapped_teras design in the MPW5 open ASIC flow. It allows VHDL-generated arithmetic to enter a flow that expects Verilog.
Conversion is limited by GHDL’s synthesis support. Unsupported VHDL constructs require changes to the input design or toolchain; the wrapper is not a complete VHDL-to-Verilog language translator.