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Academic appointments, teaching, publications, and software. A PDF version is available below.

Profile

Associate Professor (Maître de conférences) · Université de Rennes / ISTIC · IRISA / Inria Taran

Research in computer arithmetic, compiler transformations, and hardware architectures.

i.f.lledoux[at]gmail.com · +33 [seven] 70 49 11 98

LinkedIn · Twitter · GitHub · ORCID · Google Scholar

Experience

  • 2026.08 - Now

    Associate Professor (Maître de conférences)

    Université de Rennes – ISTIC / IRISA / Inria Taran

    Teaching-and-research faculty member (enseignant-chercheur) at ISTIC, Université de Rennes, with research in IRISA's Architecture Department (D3) as a member of the Inria Taran project-team.

    • Contributing to the design and tapeout of AI accelerators within the national PEPR CAMELIA program.
    • Designing systolic-array and tensor architectures with small-format floating-point arithmetic.
  • 2025.01 - 2026.07

    Postdoctoral Researcher

    INSA/INRIA – Emeraude

    Researched arithmetic compilation and optimization using MLIR, HAriCo/FloPoCo, CIRCT, Faust, and open EDA flows.

    • Developed multi-level arithmetic transformations from real-valued expressions to fixed-point polynomial approximations for ASIC and FPGA targets.
    • Extended MLIR with custom dialects to support arithmetic abstraction, reasoning, and approximation.
    • Automated the generation of hardware architectures directly from DSP-oriented code (e.g., Faust), enabling end-to-end lowering from mathematical expressions to silicon.
    • Contributed to the refactoring of FloPoCo toward explicit IR-based circuit generation, in connection with HAriCo/CIRCT-compatible lowering.
    • Presented results at DSD 2025, EuroLLVM 2025, the PEPR IA Embarquee workshop in Aussois (2026), and EuroLLVM 2026.
  • 2018.08 - 2024.12

    Researcher

    Barcelona Supercomputing Center (BSC) - RoMoL/CAOS/SONAR

    As a BSC researcher during my PhD, I published peer-reviewed papers, attended international conferences, and developed software toolchains and hardware designs for numerical acceleration.

    • Thesis: Floating-Point Arithmetic Paradigms for High-Performance Computing: Software Algorithms and Hardware Designs.
    • Explored co-designed hardware/software acceleration of posit arithmetic for FPGA and ASIC technologies, and POWER9 hosts.
    • Developed Kulisch/Quire accumulators for any floating-point representation.
    • Conducted accuracy and energy budgeting tailored to workload numerical requirements.
    • Designed Systolic Array architecture for HPC workloads with three directions of data flow, infinite number representations, and tailored internal precision.
    • Proposed serialized, area-efficient division units targeting the SIMD/Vector paradigm at the architecture level, further improving the parallelism/latency/energy ratio.
  • 2017.08 - 2018.07

    Hardware Engineer

    b<>com

    Engaged in R&D focused on FPGA acceleration in the cloud. Successfully integrated an IP for real-time SDR to HDR video conversion, developed the IP integration using HDLs, and tweaked PCI-e drivers to maximize bandwidth.

    • Deployed a custom IP core for real-time SDR to HDR video conversion on cloud-based FPGAs.
    • Optimized PCI-e drivers, achieving sustained data transfer rates of up to 15.8 GB/s, maximizing hardware utilization and performance.
    • Evaluated nascent FPGA cloud platforms such as Amazon AWS f1 with a focus on virtualization and partial reconfiguration.
    • Integrated with OpenCL with pipelining of nvme writing/reading, FPGA writing/reading with multithreaded FIFOs.
  • 2017.07 - 2017.08

    Back End Developer

    WaryMe

    Developed the entire back end of a people security application. Ensured secure data transmission and deployed the application on AWS.

    • Developed backend services and APIs.
    • Deployed and managed the application on AWS.
  • 2016.07 - 2016.07

    Back End Developer

    ASKIA

    During this summer internship, I developed an automated CLI tool for publishing surveys on popular platforms.

    • Designed a REST API in Node.js to handle event-driven, asynchronous processes efficiently.
    • Implemented Test-Driven Development (TDD) using frameworks like Jasmine, ensuring flow verification in an environment-agnostic manner with a focus on mock and stub methodologies.
    • Enhanced security by deploying HTTPS with Let's Encrypt for secure data transmission.
  • 2014.07 - 2014.07

    Electronics Technician

    Radio Electronique Rennaise (R.E.R)

    Responsible for repairing various electronic devices, with an emphasis on audio equipment.

    • Repaired various electronic devices, focusing on audio equipmenters.
    • Soldered and reverse engineered amplifier circuits.

Education

  • 2018 - 2024

    Barcelona, Spain

    PhD

    Universitat Politècnica de Catalunya (UPC)

    Computer Architecture

    Thesis: Floating-Point Arithmetic Paradigms for High-Performance Computing: Software Algorithms and Hardware Designs. Thesis tutor: Marc Casas. Jury attributed the grade of excellent.

  • 2015.09 - 2018.06

    Rennes, France

    Engineer diploma and Master's degree

    Université de Rennes

    Computer Science

    Completed a three-year program culminating in an Engineer diploma and a Master's degree.

  • 2013.09 - 2015.06

    Rennes, France

    Classe Préparatoire

    Université de Rennes

    Mathematics and Computer Sciences

    Intensive program with a strong emphasis on Mathematics and Computer Sciences.

Teaching

  • Total teaching load: 100h.
  • 2026.08 - 2026.08

    A Coruña, Spain

    Course Instructor - Digital Design with MLIR and CIRCT

    ACM Europe School on MLIR 2026

    Designed and delivered a 1h45 interactive course for an international audience, using quizzes and guided exercises to teach digital-design fundamentals and practical MLIR/CIRCT flows: IR lowering, optimization, equivalence checking, logic synthesis, and SystemVerilog generation. Developed a capstone in which participants lowered E4M3 floating-point multiplication from arith.mulf to hw/comb circuitry; demonstrated the end-to-end path from MLIR input to a small Sky130 ASIC GDSII layout, alongside a taped-out TinyTapeout GF0P2 design.

  • 2026.01 - 2026.12

    Lyon, France

    Long-Term Project in Compilation (PLD-COMP)

    INSA Lyon

    Supervision of long-term group projects on compiler design and implementation, covering intermediate representations, program analysis, and backend code generation.

    • Level: 2nd year of engineering school / Master 1 (Computer Science, INSA 4IF).
    • Teaching load: 36h.
  • 2026.01 - 2026.12

    Lyon, France

    Operating Systems (SYS)

    INSA Lyon

    Core operating system mechanisms, including kernel and system calls, process scheduling, virtual memory, concurrency, and file systems.

    • Level: 1st year of engineering school / Bachelor equivalent (Computer Science, INSA 3IF).
    • Teaching load: 16h.
  • 2026.01 - 2026.12

    Lyon, France

    Computer Architecture (ARC)

    INSA Lyon

    Practical sessions in computer architecture for the Telecommunications curriculum, covering instruction execution, pipelining, cache memories, performance evaluation, and RISC-V assembly programming.

    • Level: 1st year of engineering school (Telecommunications track, 3TC).
    • Teaching load: 24h.
  • 2025.09 - 2026.06

    Lyon, France

    Digital Design (AC)

    INSA Lyon

    Exercises and guided sessions on digital circuit design, including combinational and sequential logic, finite state machines, and introductory hardware description languages.

    • Level: 1st year of engineering school / Bachelor equivalent (Computer Science, INSA 3IF).
    • Teaching load: 12h.
  • 2025.09 - 2026.06

    Lyon, France

    Computer Architecture (AO)

    INSA Lyon

    Problem-solving and practical sessions on processor organization and instruction set architectures, based on the MSP430 microcontroller, including instruction execution, addressing modes, and memory hierarchy.

    • Level: 1st year of engineering school / Bachelor equivalent (Computer Science, INSA 3IF).
    • Teaching load: 12h.

Journal articles

Conference papers

Tutorials, workshops, and demos

Contributions to publications

Posters

Talks and seminars

Peer reviewing

Conference organisation

  • 2025.05

    Journées de l'Informatique Musicale

    Conference Organization Experience - Lyon, France (2025)

    Technician. Responsible for sound, YouTube streaming, and microphone management.

  • 2025.05

    Linux Audio Conference

    Conference Organization Experience - Lyon, France (2025)

    Technician. Responsible for sound, YouTube streaming, and microphone management.

  • 2020.04.16

    HotChips 32nd

    Conference Organization Experience - Remote (Digital), SARS-CoV-2 Period (2020)

    Remote Assistant. Assisted with digital entrance management, conference link distribution, and attendee support during the event.

  • 2019.09.09

    Field-Programmable Logic Conference 29th

    Conference Organization Experience - Barcelona, Spain (2019)

    Reception and Entrance Coordinator. Managed reception desk activities, including badge distribution and providing microphones for speakers during presentations.

Summer schools and workshops

Mentoring

  • 2026

    Esteban Wybouw

    Internship Mentoring

    Porting FloPoCo to HAriCo: an IR-based core generation framework for multi-HDL hardware generation. Co-supervised with Florent de Dinechin and Pierre Cochard.

Software and hardware

  • Software

    Open-source software for ASIC flow orchestration, numerical hardware generation, and compiler-facing exports.

    • SUF: OpenROAD-based ASIC design-space exploration and flow orchestration.
    • OSFNTC: numerically-tailored GEMM generator with PyTorch/NumPy/OpenBLAS/OpenCAPI integration.
    • MLModelMLIRGEN: PyTorch/torchvision to MLIR exporter.

  • Hardware IP

    Arithmetic IP and circuit-generation work for FPGA, ASIC, and IR-oriented hardware flows.

    • POF: SystemVerilog Posit operators, datapaths, quires, and verification benches.
    • FloPoCo: Virtex UltraScale+ timing model, systolic-array generator work, and HAriCo/IR-oriented refactoring.

  • Utilities

    Bridges and visualization utilities for open ASIC flows and research artifacts.

    • VH2V: VHDL to Verilog bridge for open ASIC flows.
    • OpenROAD GPL: placement visualization and chip-shaping experiments.
    • gdsiistl: GDSII to STL layout visualization.
    • Codez: Typst/CeTZ annotated code figures with MLIR/Python/SystemVerilog support.

  • Upstream

    Upstream contributions to compiler, OpenCAPI, and OpenROAD ecosystems.

  • Tapeouts

    Tapeout contributions and silicon demonstrators spanning Sky130, GF180, and IHP CMOS5L.

Skills

Programming and Computer Science
C
C++
Java
Scala
Algorithm Complexity
Pipeline Overlapping
Parallel Computing
Hardware Acceleration
Performance Optimization
Numerical Methods
High-Performance Computing (HPC)
Low-Level Programming
Computer Architecture
Execution Stage
Floating-Point Unit
Kulisch Accumulators
Design-Specific Architecture
Power/energy Budgeting
Data-Aware Designs
Workload-Accuracy tailored circuits
SIMD
Vector
VLIW
Systolic Arrays
Near-/In-Memory Computing
Processor Design
Out-of-Order
RISC-V
Scripting
Python
Bash
Shell
Linux
Tcl
Dissemination
LaTeX
Matplotlib
Inkscape
Top-tier conferences article
FPGA
AMD
Altera
VHDL
Verilog
SystemVerilog
Manual Floorplaning
AmaranthHDL
Automated Pipeline
Automated circuit generation
FloPoCo
SDAccel
AWS F1
PCIe
GPU
CUDA 8
CUDA 9
OpenCL
Warp
MIMD
SIMT
Branch divergence
Coalesced Access Patterns
PTX
Tensor Cores
Version Control
Git
GitHub
GitLab
SVN
Pull Requests
branches
rebases

Languages

French
Native speaker
Spanish
Native speaker (with an honest French accent)
English
Full Proficiency