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Postdoctoral Researcher

INSA/INRIA – Emeraude

Working on arithmetic compilation and optimization within the Emeraude team, at the intersection of MLIR, HAriCo/FloPoCo, CIRCT, Faust, and open EDA/hardware flows. The research focuses on bridging high-level mathematical reasoning with low-level hardware synthesis and reproducible compiler-to-silicon validation.

• Developing multi-level arithmetic transformations from real-valued expressions to fixed-point polynomial approximations for ASIC and FPGA targets.
• Extending MLIR with custom dialects to support arithmetic abstraction, reasoning, and approximation.
• Automating the generation of hardware architectures directly from DSP-oriented code (e.g., Faust), enabling end-to-end lowering from mathematical expressions to silicon.
• Contributing to the refactoring of FloPoCo toward explicit IR-based circuit generation, in connection with HAriCo/CIRCT-compatible lowering.
• Presented results at DSD 2025, EuroLLVM 2025, the PEPR IA Embarquee workshop in Aussois (2026), and EuroLLVM 2026.

Researcher

Barcelona Supercomputing Center (BSC) - RoMoL/CAOS/SONAR

As a BSC researcher during my PhD, I published peer-reviewed papers, attended international conferences, and developed software toolchains and hardware designs for numerical acceleration.

• Thesis: Floating-Point Arithmetic Paradigms for High-Performance Computing: Software Algorithms and Hardware Designs.
• Explored co-designed hardware/software acceleration of posit arithmetic for FPGA and ASIC technologies, and POWER9 hosts.
• Developed Kulisch/Quire accumulators for any floating-point representation.
• Conducted accuracy and energy budgeting tailored to workload numerical requirements.
• Designed Systolic Array architecture for HPC workloads with three directions of data flow, infinite number representations, and tailored internal precision.
• Proposed serialized, area-efficient division units targeting the SIMD/Vector paradigm at the architecture level, further improving the parallelism/latency/energy ratio.

Hardware Engineer

b<>com

Engaged in R&D focused on FPGA acceleration in the cloud. Successfully integrated an IP for real-time SDR to HDR video conversion, developed the IP integration using HDLs, and tweaked PCI-e drivers to maximize bandwidth.

• Deployed a custom IP core for real-time SDR to HDR video conversion on cloud-based FPGAs.
• Optimized PCI-e drivers, achieving sustained data transfer rates of up to 15.8 GB/s, maximizing hardware utilization and performance.
• Evaluated nascent FPGA cloud platforms such as Amazon AWS f1 with a focus on virtualization and partial reconfiguration.
• Integrated with OpenCL with pipelining of nvme writing/reading, FPGA writing/reading with multithreaded FIFOs.

Back End Developer

WaryMe

Developed the entire back end of a people security application. Ensured secure data transmission and deployed the application on AWS.

• Developed backend services and APIs.
• Deployed and managed the application on AWS.

Back End Developer

ASKIA

During this summer internship, I developed an automated CLI tool for publishing surveys on popular platforms.

• Designed a REST API in Node.js to handle event-driven, asynchronous processes efficiently.
• Implemented Test-Driven Development (TDD) using frameworks like Jasmine, ensuring flow verification in an environment-agnostic manner with a focus on mock and stub methodologies.
• Enhanced security by deploying HTTPS with Let's Encrypt for secure data transmission.

Electronics Technician

Radio Electronique Rennaise (R.E.R)

Responsible for repairing various electronic devices, with an emphasis on audio equipment.

• Repaired various electronic devices, focusing on audio equipmenters.
• Soldered and reverse engineered amplifier circuits.

PhD

Universitat Politècnica de Catalunya (UPC)

Computer Architecture

Engineer diploma and Master's degree

Université de Rennes

Computer Science

Classe Préparatoire

Université de Rennes

Mathematics and Computer Sciences

Long-Term Project in Compilation (PLD-COMP)

INSA Lyon

Supervision of long-term group projects on compiler design and implementation, covering intermediate representations, program analysis, and backend code generation.

• Level: 2nd year of engineering school / Master 1 (Computer Science, INSA 4IF).
• Teaching load: 36h.

Operating Systems (SYS)

INSA Lyon

Core operating system mechanisms, including kernel and system calls, process scheduling, virtual memory, concurrency, and file systems.

• Level: 1st year of engineering school / Bachelor equivalent (Computer Science, INSA 3IF).
• Teaching load: 16h.

Computer Architecture (ARC)

INSA Lyon

Practical sessions in computer architecture for the Telecommunications curriculum, covering instruction execution, pipelining, cache memories, performance evaluation, and RISC-V assembly programming.

• Level: 1st year of engineering school (Telecommunications track, 3TC).
• Teaching load: 24h.

Digital Design (AC)

INSA Lyon

Exercises and guided sessions on digital circuit design, including combinational and sequential logic, finite state machines, and introductory hardware description languages.

• Level: 1st year of engineering school / Bachelor equivalent (Computer Science, INSA 3IF).
• Teaching load: 12h.

Computer Architecture (AO)

INSA Lyon

Problem-solving and practical sessions on processor organization and instruction set architectures, based on the MSP430 microcontroller, including instruction execution, addressing modes, and memory hierarchy.

• Level: 1st year of engineering school / Bachelor equivalent (Computer Science, INSA 3IF).
• Teaching load: 12h.

Reconfigurable constant multipliers: hardware models, optimization algorithm and applications

International Peer-reviewed Journal - Microprocessors and Microsystems (2026)

B. Barbe, L. Ledoux, A. Volkova, and F. de Dinechin. HAL:05510936.

Towards optimized arithmetic circuits with MLIR

International Peer-reviewed Journal - WiPiEC Journal (vol. 11, no. 1, 2025)

L. Ledoux, P. Cochard, and F. de Dinechin. Associated conference presentation at the Euromicro Conference on Digital System Design (DSD). HAL:04277512.

Frugality and circuit design for digital audio signal processing

International Peer-reviewed Journal - Revue Francophone d'Informatique et Musique (vol. 11, 2025)

M. Popoff, R. Michon, T. Risset, P. Cochard, L. Ledoux, et al. DOI:10.56698/rfim.961; HAL:05489376.

Design-space exploration of serialized floating-point division for DLP architectures

International Peer-reviewed Conference Paper - 28th Euromicro Conference Series on Digital System Design (DSD 2025)

L. Ledoux. HAL:05385247.

An open-source framework for efficient numerically-tailored computations

International Peer-reviewed Conference Paper - FPL 2023 (Gothenburg, Sweden)

L. Ledoux and M. Casas. DOI:10.1109/FPL60245.2023.00011; arXiv:2406.02579; HAL:04277512.

A generator of numerically-tailored and high-throughput accelerators for batched GEMMs

International Peer-reviewed Conference Paper - FCCM 2022 (New York, USA)

L. Ledoux and M. Casas. DOI:10.1109/FCCM53951.2022.9786164; HAL:04103774.

MLIR Summer School

Teacher - MLIR Summer School (Galicia, Spain)

CIRCT and hardware generation with MLIR.

ARITH 2026

Demo - ARITH 2026 (Fulda, Germany)

End-to-end compilation from Python matrix multiplication and activation functions to silicon, with OpenROAD EDA catching optimization opportunities in between.

Progressive Arithmetic Lowering from Tensor Kernels to Synthesizable Datapaths

Tutorial / Talk - 7th MLIR Workshop @ EuroLLVM 2026 (Dublin, Ireland)

L. Ledoux, P. Cochard, and F. de Dinechin. HAL:05594483.

Tiny Tapeout: a shared silicon tapeout platform accessible to everyone

Contribution to Publication - IEEE Solid-State Circuits Magazine (2024)

Contributor (not a listed author): manuscript drafting, academic formatting, and revisions. Evidence: github.com/mattvenn/tt-ieee-paper.

Progressive Arithmetic Optimizations: Tensor and DSP Kernels to Synthesizable Datapaths

Poster Presentation - 3rd FPGA Developers' Forum (FDF) meeting, CERN (May 27-29, 2026)

L. Ledoux, P. Cochard, and F. de Dinechin. HAL:05631193v1.

Floating-point datapaths in CIRCT via HAriCo and harico-arith-to-comb lowering

Poster Presentation - EuroLLVM Developers' Meeting 2026 (Dublin, Ireland)

L. Ledoux, P. Cochard, and F. de Dinechin. HAL:05576131.

Arithmetic lowering with Emeraude-MLIR: bridging tensor and DSP kernels to silicon datapaths

Poster Presentation - Aussois, France

L. Ledoux, P. Cochard, and F. de Dinechin. HAL:05489427.

Towards multi-level arithmetic optimizations

Poster Presentation - EuroLLVM 2025 (Berlin, Germany)

L. Ledoux, P. Cochard, L. Forget, and F. de Dinechin. HAL:05063466.

LLMMMM: large language models matrix-matrix multiplications characterization on open silicon

Poster Presentation - 11th BSC Severo Ochoa Doctoral Symposium 2024 (Barcelona, Spain)

L. Ledoux and M. Casas. HAL:04592229.

The grafted superset approach: bridging Python to silicon with asynchronous compilation and beyond

Poster Presentation - OSDA 2024 (hosted at DATE, Valencia, Spain)

L. Ledoux and M. Casas. HAL:04587458.

Open-source GEMM hardware kernels generator: toward numerically-tailored computations

Poster Presentation - 10th BSC Severo Ochoa Doctoral Symposium 2023 (Barcelona, Spain)

L. Ledoux and M. Casas. arXiv:2305.18328; HAL:04094835.

FloPoCo and MLIR: a multi-level compilation framework for many intents

Invited Talk / Seminar - Holigrail Seminar, Sorbonne University (Paris, France)

L. Ledoux and P. Cochard. HAL:05412130.

The walls and the dark silicon era: an arithmetic perspective

Invited Talk / Seminar - Inria Rennes (Team TARAN)

L. Ledoux. HAL:04823130.

Accelerating DL inference with (Open)CAPI and posit numbers

Invited Talk / Seminar - OpenPOWER Summit Europe 2019 (Lyon, France)

L. Ledoux and M. Casas. HAL:04094850.

2026

Conference Peer Reviewing

FCCM (x1), ASAP (x2).

Journées de l'Informatique Musicale

Conference Organization Experience - Lyon, France (2025)

Technician. Responsible for sound, YouTube streaming, and microphone management.

Linux Audio Conference

Conference Organization Experience - Lyon, France (2025)

Technician. Responsible for sound, YouTube streaming, and microphone management.

HotChips 32nd

Conference Organization Experience - Remote (Digital), SARS-CoV-2 Period (2020)

Remote Assistant. Assisted with digital entrance management, conference link distribution, and attendee support during the event.

Field-Programmable Logic Conference 29th

Conference Organization Experience - Barcelona, Spain (2019)

Reception and Entrance Coordinator. Managed reception desk activities, including badge distribution and providing microphones for speakers during presentations.

ACM Europe Summer School on High Performance Computing

Academic Summer Schools and Workshops - Participant

Barcelona, Spain. Attended lectures and hands-on sessions covering exascale architectures, programming models, and numerical methods.

PRACE Summer School on Heterogeneous Programming with OmpSs@FPGA

Academic Summer Schools and Workshops - Participant

Barcelona, Spain. Training on FPGA-based acceleration and heterogeneous programming using the OmpSs@FPGA model.

Xilinx Machine Learning and Artificial Intelligence Seminar

Academic Summer Schools and Workshops - Participant

Paris, France. Technical seminar focused on machine learning workloads and AI acceleration platforms.

Yale Patt's Computer Architecture Summer School

Academic Summer Schools and Workshops - Participant

Barcelona, Spain. Attended the special summer edition of Prof. Yale Patt's course on out-of-order execution and advanced microarchitectural design.

Esteban Wybouw

Internship Mentoring

Porting FloPoCo to HAriCo: an IR-based core generation framework for multi-HDL hardware generation. Co-supervised with Florent de Dinechin and Pierre Cochard.

Software

Open-source software for ASIC flow orchestration, numerical hardware generation, and compiler-facing exports.

• SUF: OpenROAD-based ASIC design-space exploration and flow orchestration.
• OSFNTC: numerically-tailored GEMM generator with PyTorch/NumPy/OpenBLAS/OpenCAPI integration.
• MLModelMLIRGEN: PyTorch/torchvision to MLIR exporter.

Hardware IP

Arithmetic IP and circuit-generation work for FPGA, ASIC, and IR-oriented hardware flows.

• POF: SystemVerilog Posit operators, datapaths, quires, and verification benches.
• FloPoCo: Virtex UltraScale+ timing model, systolic-array generator work, and HAriCo/IR-oriented refactoring.

Utilities

Bridges and visualization utilities for open ASIC flows and research artifacts.

• VH2V: VHDL to Verilog bridge for open ASIC flows.
• OpenROAD GPL: placement visualization and chip-shaping experiments.
• gdsiistl: GDSII to STL layout visualization.
• Codez: Typst/CeTZ annotated code figures with MLIR/Python/SystemVerilog support.

Upstream

Upstream contributions to compiler, OpenCAPI, and OpenROAD ecosystems.

• CIRCT PR9263 and PR9245: arithmetic lowering and HDL-oriented transforms.
• oc-accel and capi2-bsp: OpenCAPI/CAPI2 accelerator support.
• OpenROAD PR: Arch/Manjaro installer support.

Tapeouts

Tapeout contributions and silicon demonstrators spanning Sky130, GF180, and IHP CMOS5L.

• MPW5 Sky130: posit/Quire systolic array.
• TT GF0P2: Faust to MLIR to silicon soft-clipper.
• TT SKY26A: MLIR to floating-point accumulator.
• IHP BF16 and IHP IEEE754: CMOS5L floating-point lowering demonstrators.
• TT SKY25B: modified-placement demonstrator.
• MPW1 and MPW4: integration contributions.