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Postdoctoral Researcher

INSA/INRIA – Emeraude

Postdoctoral research on arithmetic-aware compilation integrating MLIR and FloPoCo.

• Multi-level arithmetic transformations from real to fixed-point approximations for ASIC/FPGA.
• Custom MLIR dialects for arithmetic abstraction, reasoning, and approximation.
• Automated generation of hardware architectures from DSP-oriented code (e.g., Faust).
• Presented results at DSD 2025, EuroLLVM 2025, and EuroLLVM 2026.

Researcher

Barcelona Supercomputing Center (BSC) - RoMoL/CAOS/SONAR

Conducting research in computer architecture, arithmetic, and HPC. Exploring co-designed hardware/software acceleration of posit arithmetic, developing Kulisch/Quire accumulators, and designing Systolic Array architecture for HPC workloads.

• Thesis: Floating-Point Arithmetic Paradigms for High-Performance Computing: Software Algorithms and Hardware Designs.
• Co-designed hardware/software acceleration of posit arithmetic.
• Developed Kulisch/Quire accumulators for any floating-point representation.
• Designed Systolic Array architecture for HPC workloads.
• Explored very slow but very little floating-point division designs for SIMD/Vector paradigms.

Hardware Engineer

b<>com

Engaged in R&D focused on FPGA acceleration in the cloud. Successfully integrated an IP for real-time SDR to HDR video conversion, developed the IP integration using HDLs, and tweaked PCI-e drivers to maximize bandwidth.

• Deployed a custom IP core for real-time SDR to HDR video conversion on cloud-based FPGAs.
• Optimized PCI-e drivers, achieving sustained data transfer rates of up to 15.8 GB/s, maximizing hardware utilization and performance.
• Evaluated nascent FPGA cloud platforms such as Amazon AWS f1 with a focus on virtualization and partial reconfiguration.
• Integrated with OpenCL with pipelining of nvme writing/reading, FPGA writing/reading with multithreaded FIFOs.

Back End Developer

WaryMe

Developed the entire back end of a people security application. Ensured secure data transmission and deployed the application on AWS.

• Developed backend services and APIs.
• Deployed and managed the application on AWS.

Back End Developer

ASKIA

During this summer internship, I developed an automated CLI tool for publishing surveys on popular platforms.

• Designed a REST API in Node.js to handle event-driven, asynchronous processes efficiently.
• Implemented Test-Driven Development (TDD) using frameworks like Jasmine, ensuring flow verification in an environment-agnostic manner with a focus on mock and stub methodologies.
• Enhanced security by deploying HTTPS with Let's Encrypt for secure data transmission.

Electronics Technician

Radio Electronique Rennaise (R.E.R)

Responsible for repairing various electronic devices, with an emphasis on audio equipment.

• Repaired various electronic devices, focusing on audio equipmenters.
• Soldered and reverse engineered amplifier circuits.

Long-Term Project in Compilation (PLD-COMP)

INSA Lyon

Supervision of long-term group projects on compiler design and implementation, covering intermediate representations, program analysis, and backend code generation.

• Level: 2nd year of engineering school / Master 1 (Computer Science, INSA 4IF).
• Teaching load: 32h.

Operating Systems (SYS)

INSA Lyon

Core operating system mechanisms, including kernel and system calls, process scheduling, virtual memory, concurrency, and file systems.

• Level: 1st year of engineering school / Bachelor equivalent (Computer Science, INSA 3IF).
• Teaching load: 16h.

Computer Architecture (ARC)

INSA Lyon

Practical sessions in computer architecture for the Telecommunications curriculum, covering instruction execution, pipelining, cache memories, performance evaluation, and RISC-V assembly programming.

• Level: 1st year of engineering school (Telecommunications track, 3TC).
• Teaching load: 24h.

Digital Design (AC)

INSA Lyon

Exercises and guided sessions on digital circuit design, including combinational and sequential logic, finite state machines, and introductory hardware description languages.

• Level: 1st year of engineering school / Bachelor equivalent (Computer Science, INSA 3IF).
• Teaching load: 12h.

Computer Architecture (AO)

INSA Lyon

Problem-solving and practical sessions on processor organization and instruction set architectures, based on the MSP430 microcontroller, including instruction execution, addressing modes, and memory hierarchy.

• Level: 1st year of engineering school / Bachelor equivalent (Computer Science, INSA 3IF).
• Teaching load: 12h.

PhD

Universitat Politècnica de Catalunya (UPC)

Computer Architecture

Engineer diploma and Master's degree

Université de Rennes

Computer Science

Classe Préparatoire

Université de Rennes

Mathematics and Computer Sciences

Arithmetic lowering with Emeraude-MLIR: bridging tensor and DSP kernels to silicon datapaths

Poster Presentation - Aussois, France

L. Ledoux, P. Cochard, and F. de Dinechin. HAL:05489427.

Floating-point datapaths in CIRCT via FloPoCo AST export and flopoco-arith-to-comb lowering

Poster Presentation - EuroLLVM Developers' Meeting 2026 (Dublin, Ireland)

L. Ledoux, P. Cochard, and F. de Dinechin.

Reconfigurable constant multipliers: hardware models, optimization algorithm and applications

International Peer-reviewed Journal - Microprocessors and Microsystems (under review)

B. Barbe, L. Ledoux, A. Volkova, and F. de Dinechin.

FloPoCo and MLIR: a multi-level compilation framework for many intents

Invited Talk / Seminar - Holigrail Seminar, Sorbonne University (Paris, France)

L. Ledoux and P. Cochard.

Towards multi-level arithmetic optimizations

Poster Presentation - EuroLLVM 2025 (Berlin, Germany)

L. Ledoux, P. Cochard, L. Forget, and F. de Dinechin. HAL:05063466.

Design-space exploration of serialized floating-point division for DLP architectures

International Peer-reviewed Conference Paper - 28th Euromicro DSD 2025 (Salerno, Italy)

L. Ledoux.

Towards optimized arithmetic circuits with MLIR

International Peer-reviewed Journal - WiPiEC Journal (vol. 11, no. 1, 2025)

L. Ledoux, P. Cochard, and F. de Dinechin. Associated conference presentation at DSD 2025; HAL:04277512.

Frugality and circuit design for digital audio signal processing

International Peer-reviewed Journal - Revue Francophone d'Informatique et Musique (vol. 11, 2025)

M. Popoff, R. Michon, T. Risset, P. Cochard, L. Ledoux, et al. DOI:10.56698/rfim.961; HAL:05489376.

The walls and the dark silicon era: an arithmetic perspective

Invited Talk / Seminar - Inria Rennes (Team TARAN)

L. Ledoux.

LLMMMM: large language models matrix-matrix multiplications characterization on open silicon

Poster Presentation - 11th BSC Severo Ochoa Doctoral Symposium 2024 (Barcelona, Spain)

L. Ledoux and M. Casas. HAL:04592229.

The grafted superset approach: bridging Python to silicon with asynchronous compilation and beyond

Poster Presentation - OSDA 2024 (hosted at DATE, Valencia, Spain)

L. Ledoux and M. Casas. HAL:04587458.

Tiny Tapeout: a shared silicon tapeout platform accessible to everyone

Contribution to Publication - IEEE Solid-State Circuits Magazine (2024)

Significant contributor (not listed author): manuscript drafting, academic formatting, and revisions. Evidence: github.com/mattvenn/tt-ieee-paper.

An open-source framework for efficient numerically-tailored computations

International Peer-reviewed Conference Paper - FPL 2023 (Gothenburg, Sweden)

L. Ledoux and M. Casas. DOI:10.1109/FPL60245.2023.00011; arXiv:2406.02579; HAL:04277512.

Open-source GEMM hardware kernels generator: toward numerically-tailored computations

Poster Presentation - 10th BSC Severo Ochoa Doctoral Symposium 2023 (Barcelona, Spain)

L. Ledoux and M. Casas. arXiv:2305.18328; HAL:04094835.

A generator of numerically-tailored and high-throughput accelerators for batched GEMMs

International Peer-reviewed Conference Paper - FCCM 2022 (New York, USA)

L. Ledoux and M. Casas. DOI:10.1109/FCCM53951.2022.9786164; HAL:04103774.

Accelerating DL inference with (Open)CAPI and posit numbers

Invited Talk / Seminar - OpenPOWER Summit Europe 2019 (Lyon, France)

L. Ledoux and M. Casas. HAL:04094850.

Tapeouts

Tapeouts across TinyTapeout and Sky130 MPW programs, including arithmetic-focused silicon demonstrators.

• TinyTapeout GF0P2: Faust -> MLIR data path with tanh saturation.
• TinyTapeout Sky130: modified placement flow and visual experimentation.
• MPW5 Sky130: posit/quire systolic array for matrix multiplication.
• Contributions to MPW1 bring-up and MPW4 re-tapeout.

Toolchains

Open-source hardware/software toolchains for numerically-tailored computation and ASIC generation.

• OSFNTC: numerically-tailored GEMM generator with PyTorch/OpenBLAS/OpenCAPI integration.
• SUF: Python -> ASIC design-space exploration flow.
• VH2V: VHDL -> Verilog translation for OpenLane/OpenROAD.
• POF: SystemVerilog posit operators framework.
• gdsiistl: GDSII -> STL conversion tooling.

Open-Source Contributions

Upstream and ecosystem contributions spanning compiler IRs, arithmetic generation, and acceleration stacks.

• CIRCT/LLVM: arithmetic dialect and HDL lowering contributions.
• OpenCAPI ecosystem: oc-accel and capi2-bsp support improvements.
• OpenROAD global placer experiments and visualization work.
• FloPoCo: Virtex UltraScale+ timing model contribution.

Technician

Journees de l'Informatique Musicale

Responsible for sound, YouTube streaming, and microphone management.

• Conference organization support.

Technician

Linux Audio Conference

Responsible for sound, YouTube streaming, and microphone management.

• Conference organization support.

Remote Assistant

HotChips 32nd

Assisted with digital entrance management, conference link distribution, and attendee support during the event.

• Conference operations support.

Reception and Entrance Coordinator

Field-Programmable Logic Conference 29th

Managed reception desk activities, including badge distribution and providing microphones for speakers during presentations.

• Conference operations support.