ARITH 2026: CIRCT Tutorial and Mathematical Intent on Silicon

At ARITH 2026, I was happy to co-run the tutorial Optimizing Datapath Circuits with MLIR and CIRCT with Sam Coward. The tutorial was part of the ARITH tutorial day, on Saturday June 27, 2026, and focused on a question I care about a lot: how compiler infrastructure can make hardware design more inspectable, transformable, and testable.

The hands-on material is available here: cowardsa/CIRCT_TUTORIAL_2026. The tutorial slides are also in the repository: CIRCT_DEMO_2026_SLIDES.pdf.

Title slide for the CIRCT Tutorial at ARITH 2026.
Tutorial slide deck: a practical entry point to CIRCT as compiler infrastructure for hardware.

The Tutorial

The ARITH tutorial page described the session as a brief overview of how compiler technologies can offer another route into EDA. In practice, that meant starting from small circuits and moving through concrete compiler operations rather than staying at the slogan level.

The material walked through:

  • parsing Verilog into CIRCT IR,
  • applying passes such as range narrowing and canonicalization,
  • checking transformations with circt-lec,
  • emitting Verilog with firtool,
  • moving toward datapath synthesis and AIGER output.

I liked this format because it made CIRCT feel less like a large infrastructure project and more like something participants could actually touch. You could edit a circuit, run a pass, ask whether the result was equivalent, and see where the hardware representation changed.

The Demo

During the ARITH demo session on Monday June 29, 2026, I also showed Printing Mathematical Intent onto Silicon with Emeraude-MLIR, HAriCo, and OpenROAD, listed in the ARITH program.

The pitch was deliberately direct: I want to keep mathematical intent visible long enough that it can influence the silicon we eventually generate. The demo connected three parts of my current stack:

  • Emeraude-MLIR to carry tensor, DSP, and arithmetic structure through progressive lowering,
  • HAriCo to materialize arithmetic circuits in a compiler-friendly way,
  • OpenROAD to make the result land in physical design rather than stop at abstract RTL.
Title slide for Printing Mathematical Intent onto Silicon, the ARITH 2026 demo by Louis Ledoux.
Demo framing: from mathematical expressions and compiler IR down to generated layouts.

One of the examples starts from Python tensor code shaped like an LLM feed-forward sublayer. Another starts from a Faust audio DSP expression. They are intentionally different front ends, but they share the same constraint: useful arithmetic structure should not disappear before the compiler has a chance to act on it.

For the visual part, I showed an OpenROAD placement animation from a generated systolic-array layout. The video is here:

Showoff video: a 6x7 FloPoCo systolic-array placement run with a modified OpenROAD visualization flow.
OpenROAD placement frame showing a colored arithmetic layout shaped like an ARITH logo.
One placement frame from the demo: physical design as both evidence and communication material.

Why I Liked Animating This

The most useful conversations around this work usually happen when the abstraction layers are visible at the same time. A tutorial makes the compiler machinery approachable. A demo makes the physical consequences tangible. ARITH was a good place to bring those two modes together: formal enough to discuss correctness and arithmetic, but close enough to the tools that people could ask practical questions about passes, verification, and layout.

That balance is exactly where I want this line of work to keep moving.

Useful links:




    Enjoy Reading This Article?

    Here are some more articles you might like to read next:

  • My Latest TinyTapeout makes MLIR Arithmetic Silicon-Visible
  • I Won the TinyTapeout Sticker Competition!
  • 90s Retro Raytracing of SKY130HD Cells with Bryce
  • Music/DJ set
  • My Take on Manim Slides